VHDL default signal state bug ?

I see.

In some VHDL book it seems that "when" implicitly creates a process that internally does "if" instead. This of course is exactly what I wanted to avoid (even though I suppose when all cases are covered the compiler can optimize out the FlipFlops that the process needs to hold the sequential states).

so instead of

load(i) <= '1' when (conv_integer(address) = i) else '0';

I'd better write something like

load(i) <= not  (conv_integer(address) xor  i);

Would this avoid the problem from ground up ?

-Michael