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I do see that the code can (or must) be interpreted in the way you mention. So my question is how to be sure that this is not happening. Do I really need to give an "else" with any assignment, so that the compiler knows that I don't want a previous result ?
-Michael
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Any code that is not clocked must have all cases covered, otherwise latches (ie. memory) are infered because it assumes there are some states you dont want it to react to, and keep the previously stored value. Latches are not good things because you cannot guarantee timing on them, and glitches are likely to occur. For example in the case above - if the individual bits in the adddress line change at a different time, you are going to set 2 output bits when you only meant to set 1.
In a clocked process, if you dont cover all cases, the register will just become a DFFE (register with enable port) with the existing conditions setting the enable port. This is safe and normally what you want, because they are timed against the clock. Use the following template - it will only load a value when enable = '1':
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
q <= d;
end if;
end if;
end process;
The most common place for people to create latches is in state machine processes when the 2-process technique is used. In this case, people often forget to assign every signal in every state. The usual way to bypass this is to assign a default value at the top of the process, or just ignore the 2-process method altogether and keep it to a single process.
Back to the origional question, there are many ways to do various things. For your example, there is another way of doing the same thing instead of using a generate loop:
process(address)
begin
load <= (others => '0');
load(conv_integer(address)) <= '1';
end process;
In this case, when address changes, load has all bits set to '0', but the address bit is overidden with a '1'. This should output the same logic as with the generate loop.
Honored Contributor
