VHDL default signal state bug ?

The second example is simply a decoder, clear combinational code without any ambiguousities.

The first example must implement latches (in a FPGA, they are created as logic loops) to hold the state of the unselected bits. You have at least the problem, that changing the select input can set additional bit's due to glitches, but never reset them. I'm also not sure, if the default expression is synthesized correctly with latches as it works with registers.