Honored Contributor
Honored ContributorOops (maybe this is a silly question, as I am new to VHDL, while the colleage of mine who does work with VHDL since some time, is not available right now. And of course this is strictly of-topic,so feel free to ignore).
>>"The second example sets every bit to '0'," When ? (My thinking was, "always, unless something else is stated", thus not time-depending but just as logical result of all lines in the module.) What exactly makes the compiler think that I want to store something with the first code and thus it needs to implement any FlipFlops, and not just logic gates ? (No clock is mentioned anywhere, RS-FF with just a set and no reset does not seem to make any sense.) Is it just because there is not "else" ? If we want to do a "synchronous" design (state changes only due to clock edges), how to make sure that no "parasitic" R/S FFs are created ? -Michael
