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Altera_Forum
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16 years ago

VHDL default signal state bug ?

We tried to do a very simple thing: a demultiplexer that enables one of several gates according to the state of an n-signal vector. (Just static, no Flipflops involved.) So we defined a 2^n sig...
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Altera_Forum
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16 years ago

From looking at the code you have posted, they are not the same thing.

The second example sets every bit to '0', and the selected address to '1' every time the address changes.

The first (non working) example is making latches. You may be inititialising all the results to '0' but you are latching a '1' into them when the address is set, and then they will stay at '1' for ever.