Hello, I'm trying to follow lab 4, but am having problems. I was just told that my TFF was garbage, and it was pretty poetic, I wish i could post it for comic-relief, but anyway, I'd like to ask what you guys think of my TFF entity myTFF is port( T, Clk, Reset : in std_logic; Q : out std_logic ); end myTFF; architecture behavioral of myTFF is signal buf : std_logic; begin process(T, Clk, Reset) begin if(reset = '1') then buf <= '0'; end if; if(Clk = '1') then if(T = '1')then buf <= (NOT buf); end if; end if; end process; Q <= buf; end behavioral; would love some feedback thanks malik

You have to look at the edge of the clock, not the level. if (clk = '1') then become if rising_edge(Clk) then About the reset, if it is asynchronous, the first test must be on it and the second on the clock (use if, elsif), else if it is synchronous the first test is on the clock and the second is on the reset.

Hmm thanks for the seggestion, but now it does nothing. I guess that takes me to my next question, Is this mess what altera was suggesting by using 16 TFFs to make the counter? :) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity TFFcounter16bit is port ( enable, clk, rst : in std_logic; Qpin : out unsigned(15 downto 0) ); end TFFcounter16bit; architecture wowee of TFFcounter16bit is signal Qout : unsigned(15 downto 0); begin myTFF0 : entity work.myTFF port map( enable, clk, rst, Qout(0)); myTFF1 : entity work.myTFF port map( (enable AND Qout(0)), clk, rst, Qout(1)); myTFF2 : entity work.myTFF port map( ((enable AND Qout(0)) AND Qout(1) ), clk, rst, Qout(2)); myTFF3 : entity work.myTFF port map( (((enable AND Qout(0)) AND Qout(1)) AND Qout(2) ), clk, rst, Qout(3)); myTFF4 : entity work.myTFF port map( ((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3) ), clk, rst, Qout(4)); myTFF5 : entity work.myTFF port map( (((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)), clk, rst, Qout(5)); myTFF6 : entity work.myTFF port map( ((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)), clk, rst, Qout(6)); myTFF7 : entity work.myTFF port map( (((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)), clk, rst, Qout(7)); myTFF8 : entity work.myTFF port map( ((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)), clk, rst, Qout(8)); myTFF9 : entity work.myTFF port map( (((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)), clk, rst, Qout(9)); myTFF10 : entity work.myTFF port map( ((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)), clk, rst, Qout(10)); myTFF11 : entity work.myTFF port map( (((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)), clk, rst, Qout(11)); myTFF12 : entity work.myTFF port map( ((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)), clk, rst, Qout(12)); myTFF13 : entity work.myTFF port map( (((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)), clk, rst, Qout(13)); myTFF14 : entity work.myTFF port map( ((((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)) AND Qout(13)), clk, rst, Qout(14)); myTFF15 : entity work.myTFF port map( (((((((((((((((enable AND Qout(0)) AND Qout(1)) AND Qout(2)) AND Qout(3)) AND Qout(4)) AND Qout(5)) AND Qout(6)) AND Qout(7)) AND Qout(8)) AND Qout(9)) AND Qout(10)) AND Qout(11)) AND Qout(12)) AND Qout(13)) AND Qout(14)), clk, rst, Qout(15)); Qpin <= Qout; end wowee;

Can you put your modified code of myTFF ?

sure: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity myTFF is port( T, Clk, Reset : in std_logic; Q : out std_logic ); end myTFF; architecture behavioral of myTFF is signal buf : std_logic; begin process(T, Clk, Reset) begin if(reset = '1') then buf <= '0'; elsif(rising_edge(Clk))then if(T = '1')then buf <= (NOT buf); end if; end if; end process; Q <= buf; end behavioral;

This is correct, except that you don't need to put T signal in the sensitivity list of the process, because the output can change only when the reset is active, or on clock edge.

VHDL: DE2 Lab4 part1 | Altera Community

13 Replies

Altera_Forum
Honored Contributor
15 years ago
In this case, what can be the interest to use an unsigned ?

I am ok that it will not change the systhesis result, but personnaly I use types according to what they do. I use std_logic_vector if it is not a number or if they is no particular operation on it, and I use signed and unsigned if the vector corresponds to a number and if I have to make arithmetic operation on it.

Altera_Forum

Honored Contributor

15 years ago

my only reason for using unsigned( that i can remember right now ) is cause it was recommended to me. Oh, and there are certain conversion functions that aren't IEEE when using std_logic_vector, that are when using unsigned. Whatever works for now :)

And thanks, I was thinking of using a T() signal but wasn't sure how I would go about implementing it. Thanks for showing me that it wasn't that complicated. Now, it seems that my HEX ROM is a little buggy. But maybe that should be in another topic, since i think i want to ask what people see is wrong with it, and what would i use to debug it.

Actually, I guess I should ask here, since it's about Lab1 :)

Here's my HEX ROM:


entity HEX is
	port( HEXcnt	: in unsigned(3 downto 0);
			HEXOut	: out std_logic_vector(6 downto 0)
	);
end HEX;
architecture behavioral of HEX is 
	
	signal HEXInt : integer;
	
	type SegROM is array (0 to 9) of std_logic_vector(6 downto 0);
	constant segStates : SegROM := (
		0 => "1000000",
		1 => "1111001",
		2 => "0100100",
		3 => "0110000",
		4 => "0011001",
		5 => "0010010",
		6 => "0000010",
		7 => "1111000",
		8 => "0000000",
		9 => "0010000",
--		others => (others => '0'));
		others => "1000000");
	
begin
	
	process(HEXcnt, HEXInt) begin
	
		HEXInt <= to_integer(unsigned(HEXcnt));
		HEXOut <= segStates(HEXInt);
	
	end process;
	
end behavioral;

when using the top-level file that i'll post below, i go from 0-9 fine, but after that, I get a backward looking 9 and 4 more characters from the array list above, as if my counter is going to 16. it is 4-bit, but i only want it to go to 9 before resetting to 0 and moving and incrementing the 10s place Seg.


entity part1 is
	port( 	KEY	 		: in std_logic;
			SW			: in std_logic_vector(1 downto 0);
			HEX0, HEX1	: out std_logic_vector(6 downto 0)
	);
end part1;
architecture behavioral of part1 is
	
	--create digits to represent the decimal number
	subtype digit is integer range 0 to 9;
	
	signal h1	: digit;
	
	--use to convert the digits to slv
	signal hv1	: unsigned(3 downto 0);
	
	signal Qout : unsigned(15 downto 0);
	signal Nout : integer;
begin
	
	cnt16 : entity work.TFFcounter16bit port map(SW(1), KEY, SW(0), Qout);
	
	seg0 : entity work.HEX port map(Qout(3 downto 0), HEX0);
	seg1 : entity work.HEX port map(hv1, HEX1);
	
	process(Nout, h1) begin
			
		if((Nout > 9) AND (Nout < 99)) then
			h1 <= h1 + 1;
		end if;
		
	end process;
	
	Nout <= to_integer(unsigned(Qout));
	
	hv1 <= to_unsigned(h1, hv1'length);
	
end behavioral;

Altera_Forum
Honored Contributor
15 years ago
silly me, I'm trying to get it to display as decimal. It's telling me to use hex. sucks really, I would have loved to make it work in decimal as well

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VHDL: DE2 Lab4 part1

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