VHDL: DE2 Lab4 part1

my only reason for using unsigned( that i can remember right now ) is cause it was recommended to me. Oh, and there are certain conversion functions that aren't IEEE when using std_logic_vector, that are when using unsigned. Whatever works for now :)

And thanks, I was thinking of using a T() signal but wasn't sure how I would go about implementing it. Thanks for showing me that it wasn't that complicated. Now, it seems that my HEX ROM is a little buggy. But maybe that should be in another topic, since i think i want to ask what people see is wrong with it, and what would i use to debug it.

Actually, I guess I should ask here, since it's about Lab1 :)

Here's my HEX ROM:

entity HEX is
	port( HEXcnt	: in unsigned(3 downto 0);
			HEXOut	: out std_logic_vector(6 downto 0)
	);
end HEX;
architecture behavioral of HEX is 
	
	signal HEXInt : integer;
	
	type SegROM is array (0 to 9) of std_logic_vector(6 downto 0);
	constant segStates : SegROM := (
		0 => "1000000",
		1 => "1111001",
		2 => "0100100",
		3 => "0110000",
		4 => "0011001",
		5 => "0010010",
		6 => "0000010",
		7 => "1111000",
		8 => "0000000",
		9 => "0010000",
--		others => (others => '0'));
		others => "1000000");
	
begin
	
	process(HEXcnt, HEXInt) begin
	
		HEXInt <= to_integer(unsigned(HEXcnt));
		HEXOut <= segStates(HEXInt);
	
	end process;
	
end behavioral;

when using the top-level file that i'll post below, i go from 0-9 fine, but after that, I get a backward looking 9 and 4 more characters from the array list above, as if my counter is going to 16. it is 4-bit, but i only want it to go to 9 before resetting to 0 and moving and incrementing the 10s place Seg.

entity part1 is
	port( 	KEY	 		: in std_logic;
			SW			: in std_logic_vector(1 downto 0);
			HEX0, HEX1	: out std_logic_vector(6 downto 0)
	);
end part1;
architecture behavioral of part1 is
	
	--create digits to represent the decimal number
	subtype digit is integer range 0 to 9;
	
	signal h1	: digit;
	
	--use to convert the digits to slv
	signal hv1	: unsigned(3 downto 0);
	
	signal Qout : unsigned(15 downto 0);
	signal Nout : integer;
begin
	
	cnt16 : entity work.TFFcounter16bit port map(SW(1), KEY, SW(0), Qout);
	
	seg0 : entity work.HEX port map(Qout(3 downto 0), HEX0);
	seg1 : entity work.HEX port map(hv1, HEX1);
	
	process(Nout, h1) begin
			
		if((Nout > 9) AND (Nout < 99)) then
			h1 <= h1 + 1;
		end if;
		
	end process;
	
	Nout <= to_integer(unsigned(Qout));
	
	hv1 <= to_unsigned(h1, hv1'length);
	
end behavioral;