VHDL Compilation problem : Quartus 11 : Error (12061):

Thanks you very much for all your answers and support. I really appreciate it. As I am new to VHDL , I was little confused about the syntax. The error was solved after I made "(3 to 0)" to "(3 downto 0)" (which was I really intended to do) then the synthesis was successful. I think I am getting familiarized with VHDL and FPGA :D . I am doing a project to implement a communication protocol in FPGA. So as to get started with VHDL, I randomly wrote that module decoder, just to understand and familiarize with VHDL. There is no practical importance to it in my project.