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Honored Contributor
Honored ContributorVHDL Compilation problem : Quartus 11 : Error (12061):
Hi friends, I am new to VHDL , FPGA and Qaurtus. I am getting having a hard time in compiling a VHDL model in Qaurtus ll web edition. The code is below. I compiled it from Modelsim , there it ...
Altera_ForumHonored Contributor
Honored ContributorIt seems that there is no top design file selected in your project.
You should start with some VHDL tutorial and looking at some other peoples code. 1. The inferred latches should not intended to be here 2. Don't know why ModelSim does not complain but also your in and output ports are all 0 ranged. You meant "3 downto 0" and not "3 to 0" 3. All what you are doing is a simple "data_out <= not data_in"
