Honored Contributor
Honored ContributorThe synthesis tool noticed that all of the if statements are in parallel, so it chooses the very last one to implement. It should reduce it to a combinatorial latch that clears all of the output bits once it sees all of the input bits set; there is no way for it to set any of the output bits.
In simulation, each if statement in turn is evaluated, and only the one where the input matches does the evaluation result in an assignment. So you have a synthesis/simulation mismatch. Your decoder is best implemented with a case statement. As for the specific errors, who can tell? Is your decoder the top level or is there something else you're not showing us? "1.What is the differance between Qaurtus ll and Model SIM ?" Quartus II is the FPGA synthesis and implementation tool. It takes your source files and your constraints and (hopefully) fits them into the specified FPGA device. ModelSim is a simulation tool. You use it to simulation and verify the individual sources and the entire design. You have to write the test benches which stimulate the design and verify its outputs. You will also need to write or obtain functional models of any external devices to which the FPGA connects. "2.Can't run test-bences in Quartus II ?" Quartus II can launch a simulation in ModelSim, but it's easier to just run ModelSim standalone with your own test benches.
