VHDL code

The first step is to have some kind of clock, a couple of time higher then the requested time intervals. What I usually do is make the design synchroneous to a masterclock.

You can evaluate "on rising edge".

I am used to the old AHDL language of Altera ( early user, late adapter....) it will look like:

DFF.clk := Global clock ; evaluate every clock pulse

DFF.d := Data == Value ; Latch result

Result := DFF.q ;

DFF2.clk := Global clock ;

DFF2.d := Result ;

Result2 := DFF2.q ; Delaye with one clock pulse

eg in hardware you are creating a delay pipeline.

Other solutions are start a counter and gate the result at a certain clock count,

Use shift registers ( which are in fact cascaded DFF's )

While writing VDL, just think in hardware!

Succes,

Andries