VHDL code

Amirster, can you take a step back and explain what you're trying to do? In the original code you had a wait of 25ns. Synthesizable VHDL doesn't have a strong concept of time. The suggestions of making a counter depend on your clock frequency, which is outside of the VHDL construct. For example, if you made a counter that waits for 5 cycles, that will be different if you feed a 10MHz clock into the system versus a 100MHz clock.

If you're looking for pure delay(and no registers), that is strongly recommended agains. There are cases where people do it, but it requires min/max setup and hold timing analysis, and can be quite complicated. I think we can answer your question better if you describe your problem from a higher level, as you most likely don't want a pure delay.