VHDL code

Hello,

wait for "time" is not a synthesizable statement. There is no kind of Hardware wich would support this.

I agree to the others here: If you need the 25 ns timing you can use a enable signal wich is derived from a clock which runs at 40 Mhz and enable the output for one clock cylce.

When I look at your code, I've got one questions to you and the community, which is a little bit off topic:

In the case statement you use large bit vectors in binary coding.

when 3186=> data_out <= ("1010101101101001110100000011011");

I would use internally a 32 bit vector and code the output vector in this way

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signal data_internal : std_logic_vector(31 downto 0);

begin

process

begin

if CLK'EVENT and CLK = '1' then

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case...

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when 3186=> data_internal <= x"55B4E81B"

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end case;

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end process;

data_out <= data_internal(30 downto 0);

end arch..;

I think this version has a better "readabiltiy". What do you think? What do the others in here think about this?

Regards Christian