VHDL code help!

This is because you declared the ports as integer without a range definition. integers will synthesise to 32 bit busses, and as the MSBs are never used, they are removed.

You should not use integers at the top level to connect to pins on the device.

There are plenty of tutorials on the internet on how to write a testbench. A testbench is just another peice of code (maybe VHDL) that provides stimulus for your design under test. Because it is not synthesised, you can write things you cannot write in VHDL code for FPGAs, eg:

signal clk : std_logic := '0';
....
clk <= not clk after 5 ns; --100 MHz