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Altera_Forum
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13 years ago

vhdl code for state machine

Hai, Can anyone justify what the different between two line codes below: 1) case cycle is when 0l1l7 =>cp<=SXT(bm,11)+b3; end case 2) if cycle=2 or cycle=3 then ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hai Daixiwen and Tricky,

Thanks for your explanations. I understand now, very appreciates. :)