Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

vhdl code for state machine

Hai, Can anyone justify what the different between two line codes below: 1) case cycle is when 0l1l7 =>cp<=SXT(bm,11)+b3; end case 2) if cycle=2 or cycle=3 then ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

| in this context is just to combine several cases in one line and avoid repeating some code.

when 0|1|7 =>cp<=SXT(bm,11)+b3;
is equivalent to
when 0 => cp<=SXT(bm,11)+b3;
when 1 => cp<=SXT(bm,11)+b3;
when 7 => cp<=SXT(bm,11)+b3;