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Altera_Forum's avatar
Altera_Forum
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18 years ago

VHDL code for Right Shift register

Hello All..

I have problem in my code. I have created code for 8 bit shift register right..

ie my input is 11001011

then in

1st clock :- output should be :- 01100101

2nd clock :- output should be :- 00110010

3rd clock :- output should be :- 00011001

4th clock :- output should be :- 00001100

5th clock :- output should be :- 00000110

6th clock :- output should be :- 00000001

7th clock :- output should be :- 00000000(Ie at the end of clock 8, it should be 0h)

Please correct my code :-

library ieee;

use ieee.std_logic_1164.all;

entity shift is

port(C, SI : in std_logic;

SO : out std_logic);

end shift;

architecture archi of shift is

signal tmp: std_logic_vector(7 downto 0);

begin

process (C)

begin

if (C'event and C='1') then

for i in 0 to 6 loop

tmp(i+1) = tmp(i);

end loop;

tmp(0) = SI;

end if;

end process;

SO = tmp(7);

end archi;

Thanks a lot

26 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Your vector is std_logic_vector(7 downto 0) Left to Right, corrrect.

    In your loop process, you are looping first with index value as 0.

    So, tmp(0+1) = tmp (0); will result in tmp(1) getting written with tmp(0).

    This will take the second from right location and load it with the right most location.

    I do not believe this will accomplish your desired shift to the right, it will move the right most value into all the locations to the left.

    You will then be loading the right most location with the SI value.

    Just draw out step by step what you are trying to do and you will see that you might want to;

    SO = tmp(0);

    for i in 1 to 7 loop

    tmp (i-1) = tmp(i);

    end loop;

    tmp(7) = SI;

    and also, where is tmp declared as a register, not just as a signal?

    Tmp needs to hold the value, right.

    I hope this helps.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    shash_satish2002, its great that you are getting responses, but my advice is that if you keep using forums to help with homework and labs, you'll never do well during your exams or in your post-university career.

    These questions can be answered by debug simulation and books...
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello Sir,

    I am sorry..But actually i am doing project in company and i am just beginner in this field but this forum help me lot.

    Thank you sir.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Shah,

    Where are you located, or, if you like, adjust your profile setting to allow mw to send you a private e-mail?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    this is a 8 bit shift register with synchronous set siso

    library ieee;

    use ieee.std_logic_1164.all;

    entity shift is

    port(C, SI, S : in std_logic;

    SO : out std_logic);

    end shift;

    architecture archi of shift is

    signal tmp: std_logic_vector(7 downto 0);

    begin

    process (C, S)

    begin

    if (C'event and C='1') then

    if (S='1') then

    tmp <= (others => '1');

    else

    tmp <= tmp(6 downto 0) & SI;

    end if;

    end if;

    end process;

    SO <= tmp(7);

    end archi;

    i want to ask the meaning of the line that is in bold and red color i.e...

    tmp <= (others => '1');
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It's a synchronous preset of the SR to all '1'.

    By the way, a signal name of tmp for the shift register is rather unimaginative, isn't it?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hello all. I have this vhdl code for 4 bit shift register and i wonder why am i not getting any reasonable output after i simulate.

    library ieee;

    use ieee.std_logic_1164.all;

    entity shift_reg is

    port (

    sin,en,clk : in std_logic;

    q : out std_logic);

    end shift_reg;

    architecture shift_reg_beh of shift_reg is

    signal shft_tmp : std_logic_vector(3 downto 0);

    begin

    PROCESS (clk,en)

    BEGIN

    IF rising_edge(clk) THEN

    IF en = '1' THEN

    q <= shft_tmp(0);

    for i in 1 to 4 loop

    shft_tmp(i-1) <= shft_tmp(i);

    end loop;

    shft_tmp(3) <= sin;

    end if;

    end if;

    end process;

    end shift_reg_beh;

    My output q and the shft_tmp will always be in red and show no sign of being overwrited by the input. Plz help me out with this code .

    thanks in advance...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    have you connected sin to something in your simulation testbench?

    is en set to '1'?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I think it has to do with 'uninitialised' registers. It looks like ModelSim RTL simulation has an issue with registers without a reset. I had a similar experience yesterday. In stead of adding a reset condition for every register, I just simulated at the Gate Level and got what I wanted ...