VHDL code for 16 to 1 mux using Nand gates

kaz, you're right about different implementation methods for the same logic finally ending up in the same gate level netlist. But in VHDL text books, it's usual to distinguish these methods systematically and to require the students to solve a given problem by using one method purely.

That's possible for the said multiplexer problem, of course. Strictly spoken, the presented solution is not pure structural, because it involves a not operator. You may want to use inverter components for a pure structural solution. But the selection bits are connected correctly so far.

For the 5 input NAND component a name NAND5 rather than NAND2 should be expected. Personally, I would prefer AND5, because positive logic seems more intuitive in my opinion.

In any case, you have to combine the outputs of the 16 AND/NAND gates to form the complete multiplexer.

I see, that the popular VHDL text book enoch o. hwang, digital logic and microprocessor design with vhdl uses also a "structural" NOT gate for it's 2-to-1 multiplexer.