Altera_Forum
Honored Contributor
12 years agoVHDL Case Statement selection with "OR"
Hi, this seems to be something basic, but I just couldn't figure it out... Would be thankful if anything can help!
I am trying to do a case statement:PROCESS(CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
CASE (SRC(4 DOWNTO 0)) IS
WHEN (5X"01" | 5X"02" | 5X"03" | 5X"04" | 5X"05" | 5X"06" | 5X"07") =>
-- Do_Something_A
WHEN (5X"08" | 5X"0B") =>
-- Do_Something_B
WHEN OTHERS =>
-- Do_Something_C
END CASE;
END IF;
END PROCESS; This is the error that I get: Error (10500): VHDL syntax error at FlexBus_IF.vhd(106) near text ")"; expecting "!", or "=>" It doesn't like the "|" in the case statement. I know I can do IF/ELSE, but I would prefer not to. Any ideas as to how to do an "OR" in the CASE? Thanks.