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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL Case Statement selection with "OR"

Hi, this seems to be something basic, but I just couldn't figure it out... Would be thankful if anything can help! I am trying to do a case statement: PROCESS(CLK) BEGIN IF (RISING_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think the unneeded parantheses are causing the problem.