VHDL aggregate error

Hello I had errors that said , "Error (10514): VHDL aggregate error at gate.vhd(47): can't determine type of aggregate -- found 0 possible types"

What does it means ? Thank you

LIBRARY ieee;

USE ieee.std_logic_unsigned.ALL;

USE ieee.numeric_std.ALL;

USE ieee.std_logic_1164.ALL;

entity gate is

port(

clk : in std_logic;

reset : in std_logic;

gate_out : out std_logic

);

end gate;

architecture gate_a of gate is

--signal reset : STD_LOGIC := '0'; -- disabled reset; TODO move this signal to port

signal timer_haut : UNSIGNED(25 downto 0) := (others => '0');

signal timer_bas : UNSIGNED(25 downto 0) := (others => '0');

signal timer_tick : STD_LOGIC;

begin

process(clk)

begin

if rising_edge(clk) then

if (reset = '1') then

timer_haut <= (others => '0');

else

timer_haut <= timer_haut + 1;

end if;

end if;

end process;

process(clk)

begin

if rising_edge(clk) then

if (reset = '1') then

timer_bas <= (others => '0');

else

timer_bas <= timer_bas + 1;

end if;

end if;

end process;

timer_tick <= '1' when (timer_haut = to_unsigned(50 * 1000 * 1000), timer_us'length) else

'0' when (timer_bas = to_unsigned(60 * 1000 * 1000), timer_us'length);

end gate_a;