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Can I use hierarchical signals to port out nets / signals in the lower level? Is there other easy way (s) to do that in VHDL. For example, I have three levels in my design. Instead of carrying large number of IO through hierarchy, I can use hierarchical signals to port them to the top level for board level debugging? Thank u
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Modelsim can use VHDL-2008 to hierarchically access signals and variables (a useful feature when filling simulation memory).
Quartus does not support VHDL-2008 hierarchical access, but you can do exactly the same thing using the SignalTap II Logic Analyzer.
Cheers,
Dave
PS. Oops ... I hit reply to what I thought was the latest message, but it was just the last message on the page ... ah well, its still a valid response, so I'll leave it here.
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