VHDL-2008 support for unconstrained arrays in records

It does not seem to be supported on Quartus 18.1

It is supported on Modelsim: "ALTERA STARTER EDITION vsim 10.5b Simulator 2016.10 Oct 5 2016", which is the one distributed with Quartus 18.1

When trying to use the following record in a file:

    type t_avst_tosink is record
        data  : std_logic_vector;
        sop   : std_logic;
        eop   : std_logic;
        valid : std_logic;
    end record t_avst_tosink;

I get the following error in quartus:

Error (10482): VHDL error at example.vhd(80): object "data" is used but not declared File: /home/user/example.vhd Line: 80
Error (10411): VHDL Type Conversion error at example.vhd(80): can't determine type of object or expression near text or symbol "t_avst_tosink" File: /home/user/example.vhd Line: 80