VGA using VHDL

this is because "and" is a logical operation, not an aggregrate operation.

If you really want to do it with an aggregrate operation, you need to write:

(red_reg, green_reg, blue_reg) <= (others => '0');

but whats wrong with 3 separate assignments?

red_reg <= (others => '0');

green_reg <= (others => '0');

blue_reg <= (others => '0');

Dear Tricky.

Thanks for your reply. I already did the same as you mention. But there is another error. The error is "Error (10316): VHDL error at vga_test.vhd(35): character ''0'' used but not declared for type "std_logic_vector". Actually I refer this coding from website before I modify it for my project. Do you have any simple VHDL coding for VGA monitor. Thanks for your reply.

library ieee;

use ieee.std_logic_1164.all;

entity vga_test is

port( clk, reset: in std_logic;

sw: in std_logic_vector(7 downto 0);

hsync, vsync: out std_logic;

red,green,blue: out std_logic_vector(7 downto 0));

end vga_test;

architecture arch of vga_test is

signal red_reg: std_logic_vector(7 downto 0);

signal green_reg: std_logic_vector(7 downto 0);

signal blue_reg: std_logic_vector(7 downto 0);

signal video_on: std_logic;

begin -- instantiate VGA sync circuit

vga_sync_unit: entity work.vga_sync

port map(clk=>clk, reset=>reset, hsync=>hsync,

vsync=>vsync, video_on=>video_on,

p_tick=>open, pixel_x=>open,

pixel_y=>open);

process(clk, reset) -- rgb buffer

begin

if (reset = '1') then

red_reg <= (others => '0') ;

green_reg <= (others => '0') ;

blue_reg <= (others => '0') ;

elsif (clk' event and clk = '1') then

red_reg <= sw;

green_reg <= sw;

blue_reg <= sw;

end if;

end process;

red <= red_reg when video_on = '1' else '0';

green <= green_reg when video_on = '1' else '0';

blue <= blue_reg when video_on = '1' else '0';

end arch;

read/green/blue are std_logic_vectors, '0' is a single bit. You need to assign the entire array:

either:

x"00" = 8 bits, all zero

(others => '0') set all bits to '0'

for minima, if you kindly. may I ask the VHDL code that has managed this? I again learned to make VHDL code for VGA but do not understand its structure because I am still a beginner. beg the goodness of his heart.

my name is wahyu, student from Indonesian.

thank you so much :)