very strange Error(10500)...

I've tried to compile the following simple code (I've numbered the strings for this post, but not in VHDL file!):

1 library IEEE;

2 use IEEE.std_logic_1164.all;

3 use IEEE.numeric_std; -- (I've used .all, and without IEEE.numeric_std as well)

4

5 entity first is

6 port (A,B,C: in std_logic; F: out std_logic);

7 end first;

8

9 architecture my_first of first is

10 signal sig_1: std_logic;

11 variable var_1: integer;

12 begin

13 F<= NOT (A AND B AND C);

14 sig_1 <= A;

15 var_1:=38;

16 end my_first;

This is just from the tutorial book. While compiling I get Error (10500): VHDL syntax error at first.vhd(15) near text ":="; expecting "(", or "'", or "."

Please, point me my mistake, as I don't see any!