verlog code error

--- Quote Start ---

Error (10137): Verilog HDL Procedural Assignment error at expr.v(15): object "pwm" on left-hand side of assignment must have a variable data type

--- Quote End ---

If you don't manage to learn Verilog syntax from the bottom, you should at least read error messages thoroughly.

An output port that is assigned in a procedural statement must be defined as reg, e.g.

output reg pwm;

or

output pwm;
reg pwm;