Verilog with ANSI-style regs, non-zero initial value is not synthesised correctly!

This came up for me around a year ago. It took a while to track it down to being a Quartus problem since the simulations passed and there were no errors or warnings in Quartus. When I mentioned it to an field applications engineer (not a direct Altera FAE, rather a local distributor FAE who happens to cover Altera), the response was "well, don't write your code like that."

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The obvious workaround is to convert the port to a wire, then use an explicit assign from a register declared internally.

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Personally, I go with initial statements because the meaning and intention are a little clearer to me. Initial statements are supported by Quartus.

module mux8 (
    output reg  y,
    input wire a,
    input wire  b,
    input wire clk);
...
    initial begin
        y = 8'd4;
    end
    always @(posedge clk) y <= a ? y : y + 1;
endmodule