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I have a verilog testbench and a testcase from a previous design and am trying to revive it using quartus II web edition software. The testbench has been successfully compiled and simulated using some other simulator long ago. All i need to do is check the integrity of the design files and do a sample simulation. I believed with minor tool specific tweaks i should be able to do it.
However, It seems like for functional simulation in quartus II, one needs to generate a vector file, which i think is significant rework. Is there any way to just be able to compile and functionally simulate any existing verilog testbench with quartus II ?
Regards.
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Hi kdesai,
it is not possible to run a verilog testbench with the Quartus build-in simulator.
You have to use a third party simulator like the web edition of modeslsim. I would not
spend too much work in converting the testbench into a vector file, because the Quartus
simulator will be removed with the next release.
Kind regards
GPK
Honored Contributor
