Verilog Synthesization

Thanks for the advice. At this point I am not sure if there will be a clock, so I was just assuming that there wouldn't and that it would change whenever the input changed. The warnings are below. The first 3 make sense because of the sensitivity list. And the others have to do with pin assignments which I haven't done yet. I just don't understand why Y1, Y2, Y3 change as they do? It does not make sense with my understanding of the logic behind and always block and blocking assignments...? Any ideas on how Quartas is working?

Warning (10235): Verilog HDL Always Construct warning at error_cancellation_filter.v(18): variable "D2" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at error_cancellation_filter.v(19): variable "D1" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at error_cancellation_filter.v(22): variable "ready" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning: No exact pin location assignment(s) for 32 pins of 32 total pins

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Warning: Found 24 output pins without output pin load capacitance assignment

Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.