Verilog Synthesization

To tell you the truth, I don't know what this will turn into. I see a bunch of latches. The whole module is asynchronous, I don't suppose by chance you're allowed to have a clock are you?

I'll take your word for it that it actually synthesizes. I'd love to see the warning message Quartus prints out when it does. Actually I'm going to try it and see what happens.

How about this: (assume X changes on the clock)

module test(
    input               clk,
    input          x, 
    output  reg    y1,
    output  reg    y2,
    output  reg    y3);
reg ready = 1'b1;
always @(posedge clk) begin
        ready   <= ~ready;
    if(ready) begin
        y3      <= y2;
        y2      <= y1;
        y1      <= x;
    end
endmodule