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Altera_Forum's avatar
Altera_Forum
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11 years ago

Verilog syntax if statement

what is the correct syntax for if statement with multiple conditions?

I've written(which works): 

always@(posedge iGO or negedge iRST)//on key press event
begin
    if(!iRST)
        go_en   <=  0;
   else if (done == 1)
    go_en <= 0;
    else
    begin
        if(iGO) //if go key pressed enable ADC
            go_en   <=  1;
    end
end

but i wonder what is the syntax to write it as: 

always@(posedge iGO or negedge iRST)//on key press event
begin
    if(!iRST or (done == 1) )
        go_en   <=  0;
    else
    begin
        if(iGO) //if go key pressed enable ADC
            go_en   <=  1;
    end
end

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    They are both functionally equivalent. Write it how you want. Just make sure you comment it well.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    the second method gives me an error, i think the error was something regarding missing semicolon, which might be caused by the or (done ==1)

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    i'm curious about both codes. the rtl view of the first one show a d flip-flop: iRST - async as reset, iGO as clk, done as data input and go_en as q.

    as mhouse1 saids, second code gives an error, i think because the "or" operator ( in verilog we have '|' ). i modified so it didn't give errors:

    module verilog_ffd(igo, irst, go, done);

    input igo;

    input irst;

    output go;

    input done;

    reg go_en;

    wire caca;

    /*

    always@(posedge igo or negedge irst)//on key press event

    begin

    if(!irst)

    go_en <= 0;

    else if (done == 1)

    go_en <= 0;

    else

    begin

    if(igo) //if go key pressed enable adc

    go_en <= 1;

    end

    end*/

    always@(posedge igo or negedge caca)//on key press event

    begin

    if(!caca)

    go_en <= 0;

    else

    begin

    if(igo) //if go key pressed enable adc

    go_en <= 1;

    end

    end

    assign go = go_en;

    assign caca = irst | (done != 1);

    endmodule

    but the rtl view show a different behavior ( as expected ): -iGO as clock, data input fixed '1', and reset is ( not iRST and done ). In the second done was an async input.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The problem is

    if(!iRST or (done == 1) )

    The logical or operator is ||