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Altera_Forum
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17 years ago

Verilog real functions and compile time

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Maybe you can help me to understand what the VHDL code does. To my understanding it assigns a 32 bit signed integer value to port y. The value to be assigned is the result of a operation of data type real that is converted to integer before assigning. The verilog code does the same, and it can be systhesized. So, where is the difference?