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Honored Contributor
Honored ContributorVerilog real functions and compile time
I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_ForumHonored Contributor
Honored ContributorI am not very familiar with VHDL but I a pretty sure that this is not sythesizable, neither in VHDL nor in Verilog. For me it looks as if you write testbench code. But a testbench is not intended to by systhesized. It's only used in simulation. What do you really want to implement in the FPGA?
