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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog real functions and compile time

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Outputs to a vector.

Example code: 

module math_real_test (
    output signed  y
) ;
    function real f_real ;
        input real x ;
        begin
            f_real = 5.74857*(x + 0.7071) ;
        end
    endfunction
    assign y = $rtoi(4096.0*f_real(1.0)) ;
endmodule
I am used to the strict typing of VHDL, so I don't know if the $rtoi is required or even necessary.