Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Verilog porting woes

I'm a VHDL guy trying to port some verilog to a cyclone3. The unmodified verilog source produces parse type errors when quartus attempts to compile it. The thing that has me confused is that com...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

It seems like Quartus Verilog doesn't like a particular construct in the macros.

It doesn't understand the part selects like {x}[16:7]. 
define S1(x) ( { {x} ^ {x}, {{x}, {x}} ^ {{x},{x}} ^ {x} } )

It should be possible to change the macros to use a different part select syntax, but hardly without some basic Verilog knowledge.