Altera_Forum
Honored Contributor
Honored Contributorverilog notes
please send verilog notes to write program using loop function like for ,while, etc.,
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorI would avoid loops unless you are creating generate loop structures. Generated loop structures are unrolled when synthesized resulting in parallel hardware. If you were looking to use a loop to sequence your hardware I would recommend using statemachines or counters to do this.
