Altera_Forum
Honored Contributor
Honored Contributorverilog notes
please send verilog notes to write program using loop function like for ,while, etc.,
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Altera_ForumHonored Contributor
Honored ContributorThat's no valid Verilog syntax. Seems like you are just guessing. Please review a Verilog text book of your choice for the correct way to write a generate-loop statement.
