verilog notes

module fulladder(

input a,b,c,

output sum,carry

);

wire s1,s2,a1,a2,a3;

xor x1(s1,a,b);

xor x2(sum,s1,c);

and a11(a1,a,b);

and a2(a2,b,c);

and a3(a3,a,c);

or o1(carry,a,b,c);

endmodule

its ordinary verilog progarm if we use for loop use to reduce the code length and also less time to design.i try in loop function

plz corect this program

module fa(a,b,c,sum,carry);

input a,b,c;

output sum,carry;

integer i,j;

for (i=0;i<=1;i=i+1);

xor(i) x(i)(s(i),a,b,c);

for(j=0;j<=2;j=j+1)

and(j) a(j) )carry, a,b,c);

endmodule