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Altera_Forum
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16 years ago

verilog no warning when input wired to submodule output?

Hi, had a hard to find bug in my design, the cause went unnoticed since Quartus 9.1WE did not give any warning/error on the problem that boils down to this: module test_v10(clk, o); input clk...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Most likely what Quartus did report was that a node had no driver, or that it was synthesizing away logic (because it wasn't connected to anything), or that it converted a tri-state buffer to an input or something. These would have been visible in the synthesis report and/or fitter report.

The code itself is not illegal. And ModelSim won't flag it as an error/warning either.

Jake