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Is the output dependent on something that might not be initialized like a flip flop or RAM in module B?
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sorry, but i don't really understand this question. There is output from module B that i need in module A.
perhaps i will just provide you guys with parts of the code to make things clear.
module A;
reg s, sq, sqe;
reg q;
reg s_length, q_length, sqe_length;
reg subset_start;
wire subset_out,subset_done;
B mod_B(q,q_length,sqe,sqe_length,subset_start,subset_out,subset_done);
always @*
begin
subset_start=0;
cS=3'd 1;
s=s_in;
s_length=5'd 1;
q=s_in;
q_length=5'd 1;
sq={s,q};
sqe=sq>>1;
sqe_length=s_length+q_length-1;
subset_start=1;
(some codes here)
case (subset_out)
1: begin
.
.
.
(some codes here)
end
0:begin
.
.
.
(some codes here)
end
end
endmodule
module B(q,q_length,sqe,sqe_length,start,out,done);
input start;
input q_length;
input q;
input sqe;
input sqe_length;
output reg out,done;
always @ (posedge start)
begin
.
.
.
(codes)
end
endmodule
as you can see, i had initialized every input to module B. i'm just wondering why i can't get any output out of it. Module B wasn't executing where it should be.
the variable "subset_start" in module A was used to trigger the always block in module B. Can i do something like this ? Or i did it in the wrong way ?
Honored Contributor
