Verilog interview questions

I do the same since I'd rather have a problem solver on my team rather than someone who can just memorize syntax/details. I don't even mind if someone accidentally mixes C and verilog for example, as long as they can demonstrate that they grasp the concept that's fine by me. When a candidate admits they they are rusty with a language I just have them jump to psuedo coding since I value problem solving over syntax.