Verilog interview questions

Like kaz said they shouldn't go too in depth. They should be looking to see if you have the concepts down, if you accidentally explain something using C or VHDL for example someone like myself would see that as a strength and that you haven't memorized the language like a robot (I prefer thinkers who can google syntax rather than robots that only know syntax :))

Since it's a phone interview I would have a verilog reference card in front of you in case you can't remember a specific verilog structure. Some interviewers actually expect you to know syntax so the card might help in those cases.... then again if they are that sadistic I'm not sure if I would want to work for them :) One of the things I asks during interviews is to explain the difference between blocking and non-blocking operators and when to use each. If they get that one wrong it usually means one of two things A) they haven't really used verilog/VHDL much or B ) they probably have poor coding habits.