Verilog interview questions

Well it depends. I have been myself on the other side and I know how it feels when changing seats. The interviewer may not be verilog or HDL expert and in that case they may have some sample code segments and ask your opinion or what is wrong (they got answers prewritten). This exercise is not easy at interviews and expect the code segments to be very simple, Or they just chat you you up about how great they are and how their products are doing well.

In general, you will need to know basics of the language use e.g. IF declaration, instantiation, variables, parameters, number formats, assignments, loops, functions, tasks. Don't worry about specific details of application area as everybody knows what they are doing now and forgets it later.

Another general advice is that when asked any question don't always think there is a hidden secret or ambush to find out.