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Altera_Forum
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14 years ago

Verilog `ifdef equivalent in VHDL

Hi I've just learned that in Verilog you can use an `ifdef statement that makes Quartus ignore the following code (until the next`endif) you can define a macro in the qsf file (or through the...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I agree about readability, although VHDL comments can clarify which pins are actually used.

Virtual pins actually consume an unconnected LE in gate level netlist, don't know why.

In my opinion, all these points aren't a sufficient reason to change the design top to Verilog.