Verilog `ifdef equivalent in VHDL

Hi FvM

Of course it can be done your way, but I don't like:

1) having lots of unused virtual pins on my top level and in every partition, the added LE's might be negligible, but as an engineer I simply don't like it.

2) Personally I find this code more readable:

--- Quote Start ---

comp:interface

port map(

l

o

n

g

l

i

s

t# ifdef dff

d

end if# ifdef srff

s

r# endif

--- Quote End ---

rather then

--- Quote Start ---

dff: if DFF gnerate

comp:interface

port map(

l

o

n

g

l

i

s

t

d

end generate

srff: if SRFF gnerate

comp:interface

port map(

l

o

n

g

l

i

s

t

s

r

end generate

--- Quote End ---

and if you get a 3rd option it's get worse...