Verilog `ifdef equivalent in VHDL

If I remember right, the technique has been mentioned in several threads before. The most simple option is to keep all optional pins in the port definition of a common top entity file.

Use version dependent generate and if statements to access one or the other pin set. I'm using this method in several projects and don't see a problem with it.

I agree, that it would be convenient to have a Verilog or C alike preprocessor with VHDL. But I didn't experience a situation where the respective problem couldn't be handled with VHDL means somwhow.