Verilog `ifdef equivalent in VHDL

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I dont understand why you would be wanting to change some pin names. These are usually fixed, with sizes configurable via generics.

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Let's say I my top component has 200 pins names.

Now I have a new board revision that one of the ICs is a little different,

for example a serial instead of a parallel interface.

Without# ifdef I will have to maintain 2 files for the top component because the number of pins is changed, I also try to keep my logic names identical to the names in the schematic, so the names will probably be spi_en Vs. bus_cmd etc...

I usually encapsulate this interface inside a component that might have other logic besides the outside world pins, such as FIFOs, CPU interface, connection with other logic blocks... without# ifdef I will need to duplicate this file also...

Any change I do to other parts of the code will have to be copy pasted to other copies of the files. I can see the mess it will cause :(

An# ifdef makes my life quite easy :). but I'm sticking with VHDL. I'm now trying to write some tcl script to do it for me. I hope to upload it when I'm done.