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Altera_Forum
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14 years ago

Verilog `ifdef equivalent in VHDL

Hi I've just learned that in Verilog you can use an `ifdef statement that makes Quartus ignore the following code (until the next`endif) you can define a macro in the qsf file (or through the...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Dave

All off these methods can be a little awkward when all you want is to change a couple of pins names in an entity with 30 - 40 pins.

anyway I think I found my answer (http://www.vhdl.org/siwg/old-hm/0135.html)and it is a NO. now I have to decide if I rather use an external preprocessor or start to learn Verilog.

I have to admit I was always convinced that anything you can do with VHDL you can do with Verilog and vica versa.

I am a little bit surprised to learn that it isn't so.