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What I'm missing in the "--synthesis translate_off " statement is that it is not conditional.
It's great if you have a bit of code that you wish to omit under some condition (synthesis verses simulation), but what happens if you want to replace a part of your design with something else?
For example lets say I wish to instantiate a DFF instead of SRFF,
In that case I will have to define the pins for the SRFF even when I'm using the generate statement for instantiating only the DFF.
I can use the same pin names for both components, but for large designs it's confusing, and then you have width mismatch etc.
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There's a few methods that I've used;
1) For simulation vs synthesis
-- altera translate_off
Modelsim only ports or code goes here
-- altera translate_on
-- synthesis read_comments_as_HDL on
-- Quartus-only code goes here (inside a comment block)
-- synthesis read_comments_as_HDL off
2) For variations in hardware functionality I use generics and generate blocks, eg., to select between single-clock or dual-clock FIFOs in a bridge component.
3) For abstraction of components that differ between families, eg. RAM blocks (altsyncram vs lpm_ram_dq), use a component definition in the code, and then a VHDL configuration to map the component to the specific memory type.
Cheers,
Dave
Honored Contributor
