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Honored Contributor

14 years ago

Verilog `ifdef equivalent in VHDL

Hi I've just learned that in Verilog you can use an `ifdef statement that makes Quartus ignore the following code (until the next`endif) you can define a macro in the qsf file (or through the...

Altera_Forum

Honored Contributor

14 years ago

the only way you could do it is with generates.

You could of course hide the generates under another level of heirarchy.

Otherwise there is no way to do it, because there is no pre-compiler in VHDL.

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Verilog `ifdef equivalent in VHDL

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